1. Field of the Invention
The present invention relates generally to a synchronous static random access memory devices and, more specifically, to a synchronous static random access memory devices in which a bit line is precharged during a precharging period before data reading is carried out.
2. Description of the Prior Art
FIG. 1 is a schematic block diagram showing a whole structure of one example of a synchronous SRAM (static random access memory) device in which operation is carried out in synchronization with a clock signal, and FIG. 2 shows a structure of one portion of a memory cell array in the SRAM device of FIG. 1.
As shown in FIG. 2, in the memory cell array 1 of FIG. 1, a plurality sets of bit line pairs BL, BL and a plurality of word lines WL are arranged intersecting with each other and a static type memory cell MC is provided at each intersection of these lines. The plurality of word lines WL are connected to a X decoder 2. The X decoder 2 receives address signals AD.sub.1 to AD.sub.i and selects one out of the plurality of word lines WL to raise the potential thereof to a "H" level. In the example of FIG. 1, one set of common data line pair CDL, CDL and one sense amplifier 4 are provided for every two sets of bit line pairs BL, BL. The two sets of the bit line pairs BL, BL are connected to the common data line pair CDL, CDL through bit line selecting transistors Q1 and Q2 or bit line selecting transistors Q3 and Q4. The sense amplifier 4 is connected between each common data line pair CDL, CDL. A bit line select signal CL1 is applied to the gates of the transistors Q1 and Q2 from a Y decoder 3 and a bit line select signal CL2 is applied to the gates of the transistors Q3 and Q4 from the Y decoder 3. The Y decoder 3 receives an address signal AD.sub.i+1 and raises either the bit line select signal CL1 or CL2 to the "H" level.
As shown in FIG. 2, each bit line pair BL, BL is coupled to the supply potential V.sub.CC through precharging transistors Q5 and Q6, respectively. A precharge signal PR is applied to the gates of the transistors Q5 and Q6. In reading data from the memory cell MC, the potential of the bit lines BL and BL should be higher than a prescribed level, otherwise a read error is generated. Therefore, in this SRAM device, a bit line precharging system is employed in which the bit lines BL and BL are precharged to a prescribed potential in the precharging period before data reading from the memory cell MC.
The reading operation of the SRAM device will be described in the following. First, when the precharge signal PR becomes "H" level, the precharging transistors Q5 and Q6 turn on. Consequently, the potential of all bit line pairs BL, BL is precharged to V.sub.CC -V.sub.TH. Here, V.sub.TH is the threshold voltage of the transistors Q5 and Q6. After the transistors Q5 and Q6 are turned off, the X decoder 2 selects one of the word lines WL in response to the address signals AD.sub.1 to AD.sub.i to raise the potential thereof to the "H" level. Consequently, the data stored in each of the memory cells MC connected to that word line is read to each of the bit lines BL or BL, whereby the potential of one of the bit line pair BL, BL falls. Thereafter, the Y decoder 3 raises either the bit line select signal CL1 or CL2 to the "H" level in accordance with the address signal AD.sub.i+1. When the bit line select signal CL1 becomes "H" level, for example, the transistors Q1 and Q2 turn on and the data on the bit lines BL and BL connected to the transistors Q1 and Q2 are read on the common data line pair CDL and CDL. Thereafter, the data on CDL and CDL are amplified by the sense amplifier 4 to be outputted. In this manner, the data DQ.sub.1 to DQ.sub.n are outputted from the memory cell array 1.
The above described synchronous type semiconductor memory device is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 256997/1985, filed on June 1, 1984 by Hitachi, Ltd. and in Japanese Patent Laying-Open Gazette No. 133094/1986, filed on Dec. 3, 1984 by Oki Electric Industry Co., Ltd. and so on.
In the conventional synchronous type semiconductor memory device shown in FIGS. 1 and 2, all bit line pairs BL, BL are precharged through the precharging transistors Q5 and Q6 in the precharging period before data reading. More specifically, in FIG. 1, for example, when the bit line pair BL, BL connected to the bit line selecting transistors Q1 and Q2 is selected by the bit line select signal CL1, the precharge and data reading are also carried out for the bit line pair BL, BL connected to the bit line selecting transistors Q3 and Q4. Therefore, unnecessary precharging and discharging are carried out for the non-selected bit line pair BL, BL, presenting an obstacle in reducing power consumption.
In some cases, as shown in FIG. 3, precharging transistors are provided for each common data line pair CDL, CDL besides the bit line precharging transistors. However, in this case also, unnecessary precharging and discharging are carried out for the non-selected bit line pair BL, BL.
Now, the differences between a synchronous SRAM and an asynchronous SRAM will be described with reference to FIGS. 4A, 4B, 5A and 5B.
FIG. 4A shows a synchronous SRAM, and FIG. 4B is a timing chart for describing the operation of the synchronous SRAM. As shown in FIGS. 4A and 4B, in the synchronous SRAM, when a synchronous signal .phi.s is at "H" level, that is, in a precharge period a bit line pair BL, BL and an input/output line pair I/O, I/ are precharged to a prescribed level through precharge transistors Q25 and Q26 and precharge transistors Q27 and Q28, respectively. At that time, although address signals are applied to an X decoder 22 and a Y decoder 23, a word line WL is not driven so that data stored in a memory cell MC is not read out on the bit line pair BL, BL.
On the other hand, when the synchronous signal .phi.s is at "L" level, the word line WL is driven by the X decoder 22 so that data stored in the memory cell MC is read out on the bit line pair BL, BL and input/output line pair I/O, I/ .
As described above, data is read out in synchronization with the synchronous signal in the synchronous SRAM. Additionally, since the precharge transistors Q25 to Q28 is turned off in a reading period, a large difference appears between potential levels of the bit lines BL and BL.
FIG. 5A shows an asynchronous SRAM, and FIG. 5B is a timing chart for describing the operation of the asynchronous SRAM.
As shown in FIGS. 5A and 5B, a synchronous signal is not applied. In the asynchronous SRAM, a memory cell MC is selected in response to inputted address signals, so that the data stored in the memory cell MC is read out on a bit line pair BL, BL and an input/output line pair I/O, I/ . Therefore, the read data is asynchronously outputted in response to change of the address signals.
Additionally, since transistors Q29 to Q32 connected to the bit line pair BL, BL and the input/output line pair I/O, I/ are always turned on, a sufficient difference is not obtained between the potential levels of the bit lines BL and BL when data is read out from the memory cell MC.